The present application is directed to the electronic fabrication arts.
Electronic devices having two or more conducting contacts (e.g., terminals) such as but not limited to transistors and resistive sensors (chemiresistors, thermistors, etc.) based on active materials (e.g., active inks) are useful for numerous applications including applications in health and environmental monitoring, and asset monitoring, among many other areas. Existing fabrication processes require numerous steps in order to pattern interconnects and conducting contacts (e.g., terminals, electrodes), the active material, and the insulation required to passivate elements of the electronic devices from the operation environment, from the fabrication environment and/or from other elements of the device.
FIGS. 1 and 2 depict known processes for the fabrication of electronic devices having two or more conducting contacts (terminals). More particularly FIG. 1 illustrates portions of a process for the fabrication of an Organic Electrochemical Transistor (OECT) at micron scale reproducibly using photolithography and dry lift off to pattern the active channel and insulator. See: Khodagholy, D et al., High Speed and High Density Organic Electrochemical Transistor Arrays, Applied Phys. Lett. 99, 163304 (2001); doi: 10.1063/1.3652912; and Khodagholy, D. et al., High Transconductance Organic Electrochemical Transistors, Nat. Commun. 4:2133 doi: 10.1038/ncomms3133 (2013), and FIG. 2 illustrates portions of an alternative process which employs photolithographic patterning of the active channel using orthogonal (perflourinated) resists. See: Zhang, S., et al., Water Stability and Orthogonal Patterning of Flexible Micro-electrochemical Transistors on Plastic. J. Mater. Chem. C, 2016, 4, 1382-1385; doi: 10.1039/C5TC03664J JMC C, 2014.
Returning to fabrication process 100 of FIG. 1, a first step 110 provides a substrate 112, and a patterned (e.g., photolithography) conductive layer 114, having a channel opening 116. In step 120 the process deposits two layers of a covering material (e.g., Parylene-C, “PaC”) 122, 124 separated by an antiadhesive 126. In step 130, patterning (e.g., by photolithography) is used to etch both layers 132. Thereafter in step 140 the process includes spin casting an active material (e.g., poly polystyrene sulfonate) into the channel 116 (see step 110), and onto the surface areas 142. Finally, in step 150, a dry peel operation is undertaken to dry peel off material to define active material and the opening in the insulator 152.
Returning to fabrication process 200 of FIG. 2, in step 210 a substrate 212 is provided, and a conductive layer 214 is photolithographically patterned to create a channel 216. In step 220 active channel material (e.g., PEDOT:PSS) is spin cast 222 including into the channel. Thereafter in step 230 patterning (e.g. photolithographic operation) and liftoff of the PEDOT:PSS for orthogonal resist is undertaken 232. Next in step 240 spin cast orthogonal resist is provided as an insulating layer 242. Finally, in step 250 patterning (e.g. photolithographic) of the orthogonal resist is performed 252.
In the approaches illustrated in FIGS. 1 and 2, tolerance for alignment of subsequent photolithographic steps means significant unwanted overlap of features producing unwanted performance degrading parasitic capacitance. These approaches also require two or more photolithographic steps to define the micron scale dimensions of the channel length, width, and opening in the insulator.
It is considered useful to provide a streamlined fabrication process for the manufacture of electronic devices having two or more conducting contacts (e.g., terminals), which also reduce parasitic capacitance of the fabricated device.